A typical data transmission system comprises a transmitter, a receiver, and some form of transmission medium for carrying a data signal from the transmitter to the receiver. A common problem that occurs in such a data transmission system is that the data signal arriving at the receiver may be distorted by Inter-Symbol Interference (ISI). That is, the timing and voltage margins at the receiver are typically dependent upon the transmitted data.
ISI generally occurs due to two mechanisms. First, the timing or voltage of a data signal presently being transmitted on any given transmission line may be affected by residual reflections from prior transmitted data signals on the same transmission line. Second, adjacent transmission lines may have electromagnetic coupling. In such a case, the timing or voltage of data signals transmitted on a given transmission line may be influenced by data signals transmitted on other adjacent transmission lines.
When testing data transmission devices or systems, the operation of such devices or systems is often measured by transmitting long sequences of random data. To some degree, the accuracy of this approach depends upon the probability of the random sequence containing a worst case data pattern. The accuracy of this approach is also dependent upon whether there is significant ISI associated with the device or system. Further, the measurement apparatus may exhibit ISI, thereby introducing an additional uncertainty. In some cases, guard-banding is employed to deal with these uncertainties.
Referring to FIG. 1, there is shown a typical apparatus 10 for testing the operation of an integrated circuit (IC) memory device 12. The apparatus 10 comprises a vector memory 14 for storing random data sequences. The vector memory 14 is connected to a transmitter 16 for transmitting the random data sequences along a transmission line 18 to the IC memory device 12. The apparatus 10 also comprises a receiver 20 for receiving data transmitted from the IC memory device 12 via the transmission line 18, and a result memory 22, connected to the receiver 20, for storing the received data. The operation of the IC memory device 12 is tested by comparing the random data sequences that are transmitted from the vector memory 14 to the IC memory device 12 for storage therein with the same random data sequences after they are transmitted from the IC memory device 12 to the result memory 22 for storage therein. It should be noted that although only one transmitter 16, transmission line 18, and receiver 20 are shown, this arrangement may be duplicated as required based upon the number of input/output (I/O) lines of the IC memory device 12 to be measured.
The apparatus 10 can also be used to attempt to measure the worst case timing and voltage margins of the IC memory device 12 by measuring the output waveforms of the random data sequences after they are transmitted from the IC memory device 12 to the result memory 22. However, since there is no way to know when a worst case random data sequence will occur, every output waveform must be measured. Also, this method is not guaranteed to find the worst case timing and voltage margins since the random data sequences may not include the worst case random data sequence. This is especially true when the outputs of the IC memory device 12 are affected by ISI. In addition, if the apparatus 10 itself has ISI, the measurement result will not accurately reflect the true worst case timing and voltage margins of the IC memory device 12.
In view of the foregoing, it would be desirable to provide a technique for determining performance characteristics of electronic devices and systems which overcomes the above-described inadequacies and shortcomings.